1. Field of the Invention
This invention relates to a method of fabricating a capacitor, and more particularly, to a method of fabricating a capacitor having a number of insulating layers interlacing with a number of conducting layer for a dynamic random access memory (DRAM).
2. Description of Related Art
Because microprocessors have become more and more powerful, and the structures and required algorithms of software applications have become more and more complicated, requirements on memory capacities have been increased as well. The current DRAM cell consists of a transfer field effect transistor (TEFT) and a storage transistor.
As shown in FIG. 1, a capacitor C of the array of capacitors on a semiconductor substrate is used to store information by charging and discharging the capacitor C. Normally, a binary 0 is stored in a capacitor if the capacitor is not charged, and a binary 1 is stored if the capacitor is charged. Dielectric material 102 is filled into the space between the lower electrode 100 and the upper electrode 101 of the capacitor C to provide a necessary permittivity. The capacitor C is electrically connected to a bit line BL, so that information can be read or written through the bit line BL by charging or discharging the capacitor C. The task of charging or discharging the capacitor C is controlled and executed through a TFET, T, which has connections from the drain to the bit line BL, from the source to the capacitor C, and from the gate to the word line WL. Signals are fed into the TFET T through the word line to control the connection between the capacitor C and the bit line BL.
In a conventional fabrication process of a DRAM of less than 1 megabyte in capacity, the capacitors are normally made in a two-dimension form, a so-called planar-type capacitor. Since a conventional planar-type capacitor requires a relatively large area for storing charges, it is not suitable for the fabrication of a DRAM with high integration, such as a DRAM of larger than 4 megabytes in capacity. For the fabrication of a highly integrated DRAM, a capacitor with a three dimensional design, such as a stacked capacitor or a trench-type capacitor, is required.
Even though a typical three dimensional capacitor, such as a stacked capacitor or a trench-type capacitor, stores more charges than a conventional planar-type capacitor, that is, it has a larger permittivity, by occupying less area on the semiconductor substrate, such a design does not meet the requirement of DRAM of a still higher capacity, such as 64 megabytes.
It is obvious that downsizing a memory cell that contains the storage capacitor leads to a decrease in the permittivity of the storage capacitor. And, the decreasing of the permittivity of the storage capacitor increases the possibility of the occurrence of soft errors due to the incident .alpha. ray as well.
In order to solve the foregoing problems, the electrode and the dielectric layer of a capacitor can be extended horizontally, and stacked vertically to form a so-called fin-type capacitor. So, the permittivity of the capacitor is increased according to the increment of the surface area of the capacitor electrode.
The foregoing problems can also be resolved by extending the electrode and the dielectric layer of a capacitor vertically to form a so-called cylindrical-type capacitor. The permittivity of the capacitor is also increased according to the increment of the surface area of the capacitor electrode.
Since the integration of DRAM keeps increasing and a DRAM cell has to be accordingly downsized, manufacturers are still looking for a fabricating method and structure of a DRAM in order to downsize the DRAM cell, and in the meantime, retain the permittivity of a storage capacitor as well.